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FEATURES Very High DC Precision 30 V max Offset Voltage 0.3 V/ C max Offset Voltage Drift 0.35 V p-p max Voltage Noise (0.1 Hz to 10 Hz) 5 Million V/V min Open Loop Gain 130 dB min CMRR 120 dB min PSRR Matching Characteristics 30 V max Offset Voltage Match 0.3 V/ C max Offset Voltage Drift Match 130 dB min CMRR Match Single Version: AD707 Available in 8-Pin Plastic Mini-DIP, Hermetic Cerdip and TO-99 Metal Can Packages, Chips and /883B Parts Available.
Ultralow Offset Voltage Dual Op Amp AD708
CONNECTION DIAGRAMS TO-99 (H) Package
Plastic (N ), and Cerdip (Q) Packages
PRODUCT DESCRIPTION
The AD708 is a very high precision, dual monolithic operational amplifier. Each amplifier individually offers excellent dc precision with the best available max offset voltage and offset voltage drift of any dual bipolar op amp. In addition, the matching specifications are the best available in any dual op amp. The AD708 sets a new standards for dual precision op amps by providing 5 V/V min open loop gain and guaranteed max input voltage noise of 350 nV p-p (0.1 Hz to 10 Hz). All dc specifications show excellent stability over temperature, with offset voltage drift typically 0.1 V/C and input bias current drift of 25 pA/C max. Both CMRR (130 dB min) and PSRR (120 dB min) are an order of magnitude improved over any available single monolithic op amp except the AD707. The AD708 is available in four performance grades. The AD708J is rated over the commercial temperature range of 0C to +70C and jis available in a plastic mini-DIP package. The AD708A and AD708B are rated over the industrial temperature range of -40C to +85C and are available in a cerdip and TO99 package. The AD708S is rated over the military temperature range of -55C to +125C and is available in cerdip and TO-99 packages. Military versions are available processed to MILSTD-883B, Rev. C.
APPLICATION HIGHLIGHTS
1. The combination of outstanding matching and individual specifications make the AD708 ideal for constructing high gain, precision instrumentation amplifiers. 2. The low offset voltage drift and low noise of the AD708 allows the designer to amplify very small signals without sacrificing overall system performance. 3. The AD708's 10 V/V typical open loop gain and 140 dB common-mode rejection make it ideal for precision applications. 4. Unmounted dice are available for hybrid circuit applications. 5. The AD708 is an improved replacement for the LT1002.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD708-SPECIFICATIONS
Model INPUT OFFSET VOLTAGE1 TMIN to TMAX Drift Long Term Stability INPUT BIAS CURRENT TMIN to TMAX Average Drift OFFSET CURRENT Average Drift MATCHING CHARACTERISTICS2 Offset Voltage TMIN to TMAX Offset Voltage Drift Input Bias Current TMIN to TMAX Common-Mode Rejection TMIN to TMAX Power Supply Rejection TMIN to TMAX Channel Separation INPUT VOLTAGE NOISE VCM = 0 V TMIN to TMAX Conditions
(@ +25 C and
Min
15 V dc, unless otherwise noted)
Min AD708B Typ Max 5 15 0.1 0.3 0.5 1.0 10 0.1 0.2 1 50 65 0.4 1.0 2.0 25 1.0 1.5 25 50 75 0.4 1.0 2.0 130 130 120 120 140 0.6 18 13.0 11.0 35 0.9 0.27 0.18 130 130 5 5 120 120 0.5 0.15 140 130 130 120 120 140 0.6 12 11.0 11.0 35 0.8 0.23 0.17 130 130 4 4 120 120 0.5 0.15 140 Min AD708S Typ Max 5 15 0.1 0.3 0.5 1.0 10 0.1 0.2 1 30 50 0.3 1 4 30 1 1.5 25 30 50 0.3 1.0 2.0 Units V V V/C V/Month nA nA pA/C nA nA pA/C V V V/C nA nA dB dB dB dB dB V p-p nV/Hz nV/Hz nV/Hz pA p-p pA/Hz pA/Hz pA/Hz dB dB V/V V/V dB dB MHz V/s M G V V V V
AD708J/A Typ Max 30 50 0.3 0.3 1.0 2.0 15 0.5 2.0 2 100 150 1.0 2.5 4.0 40 2.0 4.0 60 80 150 1.0 4.0 5.0
120 110 110 110 135
140
0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz VCM = 13 V TMIN to TMAX VO = 10 V RLOAD 2 k TMIN to TMAX VS = 3 V to 18 V TMIN to TMAX 120 120 3 3 110 110 0.5 0.15
0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 10 10 130 130 0.9 0.3 60 200
0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 10 10 130 130 0.9 0.3 200 400 13.5 12.5 12.0 12.0 14.0 13.0 12.5 13.0 60
0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 10 7 130 130 0.9 0.3 200 400 13.5 12.5 12.0 12.0 14 13 12.5 13 60
0.35 12 11 11 35 0.8 0.23 0.17
INPUT CURRENT NOISE
COMMON-MODE REJECTION RATIO OPEN-LOOP GAIN
POWER SUPPLY REJECTION RATIO FREQUENCY RESPONSE Closed Loop Bandwidth Slew Rate INPUT RESISTANCE Differential Common Mode OUTPUT VOLTAGE
RLOAD 10 k RLOAD 2 k RLOAD 1 k RLOAD 2 k TMIN to TMAX
13.5 12.5 12.0 12.0
14 13.0 12.5 13.0 60
OPEN-LOOP OUTPUT RESISTANCE
-2-
REV. B
AD708
Model POWER SUPPLY Quiescent Current Power Consumption Conditions Min AD708J/A Typ Max 4.5 135 12 5.5 165 18 18 Min AD708B Typ Max 4.5 135 12 5.5 165 18 18 Min AD708S Typ Max 4.5 135 12 5.5 165 18 18 Units mA mW mW V
VS = 15 V No Load VS = 3 V
Operating Range
3
3
3
NOTES 1 Input offset voltage specifications are guaranteed after 5 minutes of operation at T A = +25C. 2 Matching is defined as the difference between parameters of the two amplifiers. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V Internal Power Dissipation2 Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and -VS Storage Temperature Range (Q, H) . . . . . . . -65C to +150C Storage Temperature Range (N) . . . . . . . . . -65C to +125C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics 8-Pin Plastic Package: JC = 33C/Watt, JA = 100C/Watt 8-Pin Cerdip package: JC = 30C/Watt, JA = 110C/Watt 8-Pin Metal Can Package: JC = 65C/Watt, JA = 150C/Watt. 3 For supply voltages less than 22 V, the absolute maximum input voltage is equal to the supply voltage.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm). Contact factory for latest dimensions.
ORDERING GUIDE
Model AD708JN AD708AQ AD708BQ AD708SQ AD708AH AD708BH AD708SH AD708SH/883B AD708J Grade Chips AD708S Grade Chips
Temperature Range 0C to +70C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C -55C to +125C
Package Description 8-Pin Plastic DIP 8-Pin Cerdip 8-Pin Cerdip 8-Pin Cerdip 8-Pin Header 8-Pin Header 8-Pin Header 8-Pin Header Die Die
Package Option* N-8 Q-8 Q-8 Q-8 H-08A H-08A H-08A H-08A
*N = Plastic DIP; Q = Cerdip; H = Hermetic Metal Can.
REV. B
-3-
AD708-Typical Characteristics (V =
S
15 V and TA = +25 C unless otherwise noted)
-4-
REV. B
AD708
REV. B
-5-
AD708-Matching Characteristics
Figure 18. Typical Distribution of Offset Voltage Match
Figure 19. Typical Distribution of Offset Voltage Drift Match
Figure 20. Typical Distribution of Input Bias Current Match
Figure 21. Typical Distribution of Input Offset Current Match
Figure 22. PSRR Match vs. Temperature
Figure 23. CMRR Match vs. Temperature
Crosstalk from Thermal Effects of Power Dissipation
Figure 24. Crosstalk with No Load
Figure 25. Crosstalk with 2 k Load
Figure 26. Crosstalk under Forced Source and Sink Conditions
-6-
REV. B
AD708
CROSSTALK PERFORMANCE OF THE AD708
The AD708 exhibits very low crosstalk as shown in Figures 24, 25 and 26. Figure 24 shows the offset voltage induced in side B of the AD708 when side A's output is moving slowly (0.2 Hz) from -10 V to +10 V under no load. This is the least stressful situation to the part since the overall power in the chip does not change; only the location of the power in the output devices changes. Figure 25 shows side B's input offset voltage change when side A is driving a 2 k load. Here the power is being changed in the chip with the maximum power change occurring at 7.5 V. Figure 26 shows crosstalk under the most severe conditions. Side A is connected as a follower with 0 V input, and is now forced to sink and source 5 mA of output current (Power = (30 V) (5 mA) = 150 mW). Even this large change in power causes only an 8 V (linear) change in side B's input offset voltage.
OPERATION WITH A GAIN OF -100
To show the outstanding dc precision of the AD708 in real application, Table I shows an error budget calculation for a gain of -100 configuration shown in Figure 27.
Table I. Maximum Error Contribution AV = 100 (S Grade) (Full Scale: VOUT = 10 V, VIN = 100 mV) 30 V/100 mV (100 k)(1 nA)/10 V 10 V/(5*106))/100 mV 0.35 V/100 mV (0.3 V/C)/100 mV = 300 ppm = 10 ppm = 20 ppm = 4 ppm = 3 ppm/C = 334 ppm +3 ppm/C Total Unadjusted Error With Offset Calibrated Out @ 25C -55C to +125C @ 25C -55C to +125C = 334 ppm > 11 Bits = 634 ppm > 10 Bits = 34 ppm > 14 Bits = 334 ppm > 11 Bits
Figure 28. Precision PGA
Error Sources VOS IOS Gain (2 k load) Noise VOS Drift
are controlled by the select lines, A0 and A1 of the AD7502 multiplexer, and are 1, 10, 100 and 1000 in this design. The input stage attains very high dc precision due to the 30 V maximum offset voltage match of the AD708S and the 1 nA maximum input bias current match. The accuracy is maintained over temperature because of the ultralow drift performance of the AD708. The output stage uses an AD707J and well matched resistors configured as a precision subtracter. To achieve 0.1% gain accuracy, along with high common-mode rejection, the circuit should be trimmed as follows: To maximize common-mode rejection: 1. Set the select lines for Gain = 1 and ground VINB. 2. Apply a precision dc voltage to VINA and trim RA until VO = -VINA to the required precision. 3. Next connect VINB to VINA and apply an input voltage equal to the full-scale common-mode expected. 4. Trim RB until VO = 0 V. To minimize gain errors: 1. Select Gain = 10 with the control lines and apply a differential input voltage. 2. Adjust the 100 potentiometer such that VO = 10 VIN (adjust VIN magnitude as necessary). 3. Repeat for Gain = 100 and Gain = 1000, adjusting 1 k and 10 k potentiometers, respectively.
Figure 27. Gain of -100 Configuration
This error budget assumes no error in the resistor ratio and no error from power supply variation (the 120 dB minimum PSRR of the AD708S makes this a good assumption). The external resistors can cause gain error from mismatch and drift over temperature.
High Precision Programmable Gain Amplifier
The design shown should allow for 0.1% gain accuracy and 0.1 V/V common-mode rejection when 1% resistors and 5% potentiometers are used.
BRIDGE SIGNAL CONDITIONER
The three op amp programmable gain amplifier shown in Figure 28 takes advantage of the outstanding matching characteristics of the AD708 to achieve high dc precision. The gains of the circuit REV. B -7-
The AD708 can be used in the circuit in Figure 29 to produce an accurate and inexpensive dynamic bridge conditioner. The low offset voltage match and low offset voltage drift match of the AD708 combine to achieve circuit performance better than all but the best instrumentation amplifiers. The AD708's outstanding specs: open loop gain, input offset currents and low input bias currents, do not limit circuit accuracy.
AD708
As configured, the circuit only requires a gain resistor, RG, of suitable accuracy and a stable, accurate voltage reference. The transfer function is: VO = VREF [R/(R+R)][RG/R] and the only significant errors due to the AD708S are: VOSout = (VOSmatch)(2RG/R) = 30 mV VOSout(T) = (VOSdrift)(2RG/R) = 0.3 mV/C To achieve high accuracy, the resistor RG should be 0.1% or better and have a low drift coefficient.
Figure 31. Absolute Value Circuit Performance (Input Signal = 0.05 Hz)
SELECTION OF PASSIVE COMPONENTS
To takc full advantagc of thc high precision and low drift characteristics of the AD708, high quality passive components must be used. Discrete resistors and resistor networks with temperature coefficients of less than 10 ppm/C are available from Vishay, Caddock, PRP and others.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Figure 29. Bridge Signal Conditioning Circuit
TO-99 (H) Package
Figure 30. Precision Absolute Value Circuit
PRECISION ABSOLUTE VALUE CIRCUIT
Cerdip (Q) Package
Mini-DIP (N) Package
Maximum error at 25C
30 V + (10 k) (1nA) = 40 V/10V = 4 ppm Maximum 10V error at +125C or -55C
50 V + (2 nA) (10 k) = 7 ppm @ +125C 10V
Figure 31 shows VOUT vs. VIN for this circuit with a 3 mV input signal at 0.05 Hz. Note that the circuit exhibits very low offset at the zero crossing. This circuit can also produce VOUT = -|VIN| by reversing the polarity of the two diodes. -8- REV. B
PRINTED IN U.S.A.
The AD708 is ideally suited to the precision absolute value circuit shown in Figure 30. The low offset voltage match of the AD708 enables this circuit to accurately resolve the input signal. In addition, the tight offset voltage drift match maintains the resolution of the circuit over the full military temperature range. The AD708's high dc open loop gain and exceptional gain linearity allows the circuit to perform well at both large and small signal levels. In this circuit, the only significant dc errors are due to the offset voltage of the two ampliliers, the input offset current match of the amplifiers, and the mismatch of the resistors. Errors associated with the AD708S contribute less than 0.001% error over -55C to +125C.
C1252a-10-2/91

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